1. Field of the Invention
The present invention generally relates to a method of forming patterns, and particularly to an improved method of forming patterns achieving a higher overlay accuracy. The present invention further relates to a photomask used for such a method of forming patterns. The present invention further relates to a method of forming a semiconductor device.
2. Description of the Background Art
In manufacturing semiconductor integrated circuits (semiconductor devices), an underlayer such as a semiconductor substrate is now selectively processed by the etching and ion implantation. In order to selectively protect the portions to be processed of the underlayer, patterns of the composition photosensitive to the source of active rays such as ultraviolet ray, x-ray, and electron beam, or of what is called photosensitive resist film (hereinafter referred to as resist) are formed on the underlayer.
The most common method of forming the resist patterns employs a reduction-type projection aligner (stepper) using as a source of rays g-line (wavelength 436 nm), i-line (wavelength 365 nm) or KrF excimer laser (wavelength 248 nm) to radiate ultraviolet ray.
When the stepper is used, a photomask is attached for exposure. The photomask is formed of a glass substrate on which a circuit pattern is formed by a blocking film such as the one formed of chromium (Cr). The photomask is referred to as reticle. In exposure, a precise overlay (registration) is required in order to correctly define the positional relation between the photomask and the circuit pattern which has already been generated on the substrate.
The pattern drawn at the photomask is reduced through a lens to be transferred onto a resist film applied onto a semiconductor substrate. Development of the resist film generates a resist pattern.
There are a positive resist and a negative resist. The positive resist has a portion on exposure to light which is dissolved in a developer and a portion not on exposure to light which is not dissolved in the developer. The negative resist has a portion on exposure to light which is not dissolved in the developer and a portion not on exposure to light which is dissolved in the developer.
The process of generating the resist pattern normally needs to be repeated 20-30 times for manufacturing a semiconductor integrated circuit device.
The higher integration and the higher performance of a semiconductor integrated circuit are being dramatically achieved now. Accordingly, further miniaturization of a circuit pattern is required. For example, in the 16-Mbit DRAM (Dynamic Random Access Memory) which is currently mass-produced, a resist pattern close to 0.4 .mu.m is formed. A photolithography process applied for the generation of the resist pattern chiefly uses i-line in the ultraviolet ray.
For the 64-Mbit DRAM, mass production of which being started, requires a pattern of 0.35-0.3 .mu.m. The 256-Mbit DRAM and the 1-Gbit DRAM in the stage of trial production or study and development need a pattern of 0.2 .mu.m or less. For generating such a minute pattern, KrF excimer laser beam is practically used. Further, exposure by ArF excimer laser beam of a shorter wavelength (wavelength 193 nm) is considered to be effective.
As the pattern is miniaturized, enhancement of dimension accuracy and overlay accuracy is required. For example, a device having a capacity on the level with 256-Mbit DRAM needs dimension control of approximately .+-.0.03 .mu.m relative to designed dimension as well as the overlay accuracy of approximately 0.06 .mu.m. Such requirements will become severer.
The factors of degradation of the overlay accuracy are a magnification error of the exposure lens, a rotational error between a photomask (hereinafter referred to as reticle) and a chip formed already on a wafer, a measurement error in overlay inspection, and the like. However, the performance of the lens and the wafer stage of an exposure apparatus as well as the performance of an overlay measurement apparatus are improved and the overlay accuracy is being improved.
As the required precision in the overlay accuracy becomes severer, an error generated during manufacturing of the reticles has a larger influence on the overlay accuracy. In addition, as the degree of integration improves, an area where the pattern is drawn and the number of data of graphics increase to dramatically increase the time required for pattern generation by electron beam (EB) in manufacturing the reticle. As the degree of integration improves, it becomes difficult to restrict the error produced during reticle fabrication due to the influence of uniformity of resist application, development, and etching within the surface.
Next, a conventional method of forming patterns using one reticle for one process is described.
FIG. 39 is a plan view of a first reticle 19 used for exposure of a pattern of a contact hole. In the first reticle 19, a contact hole pattern 2 is drawn by electron beam.
FIG. 40 is a plan view of a second reticle 21 used for exposure of a pattern of an interconnection line connected electrically to the contact hole and other interconnection line patterns. Interconnection patterns 3b and 3e are formed by light blocking portions in the second reticle 21. An opening 3c is formed between interconnection patterns 3b and 3e. A part of interconnection pattern 3e has a larger interconnection width. The portion having the larger interconnection width corresponds to a portion connected to a contact. The interconnection width is made large in advance in order to give a margin.
A method of manufacturing a conventional semiconductor device using these reticles is next described.
Referring to FIG. 41, a silicon oxide film 5 is formed on a semiconductor substrate (e.g. silicon wafer) 4 to a thickness of approximately 3000 .ANG.. A commercial KrF excimer positive resist film 10 is next applied thereon to a thickness of approximately 7000 .ANG.. Using the first reticle 19 having contact hole pattern 2, exposure is performed by a stepper with KrF excimer laser (wavelength 248 nm) 11 as a source of rays. The exposure generates a latent image of the contact hole pattern in KrF excimer positive resist film 10.
Referring to FIG. 42, after bake at 110.degree. C. for 90 seconds (post exposure bake: PEB), development performed for 60 seconds using an aqueous solution containing 2.38% tetramethyl ammonium hydroxide (TMAH) by weight produces a resist pattern 10c having an opening.
Referring to FIG. 43, silicon oxide film 5 is anisotropically etched using resist pattern 10c as an etching mask to form a contact hole 5a in silicon oxide film 5.
Referring to FIGS. 43 and 44, resist pattern 10c is removed by oxygen plasma ashing.
Referring next to FIGS. 44 and 45, metal interconnection material 12 such as tungsten silicide (WSi.sub.2) is deposited to a thickness of about 1000 .ANG. by sputtering or CVD. At this time, the metal interconnection material fills the inside of contact hole 5a.
Referring to FIG. 46, KrF excimer positive resist film 10 is again formed on semiconductor substrate 4. Exposure by the KrF excimer laser stepper is next performed using the second reticle 21 having interconnection patterns 3b and 3e drawn as shown in FIG. 40. Consequently, a latent image of the interconnection pattern is formed in KrF excimer positive resist film 10.
After bake at 110.degree. C. for 90 seconds (PEB), development performed for 60 seconds using the aqueous solution containing 2.38% tetramethyl ammonium hydroxide (TMAH) by weight generates a resist pattern 10d in the form of the interconnection on semiconductor substrate 4 as shown in FIG. 47.
Referring to FIGS. 47 and 48, the layer of metal interconnection material 12 is anisotropically etched using resist pattern 10d as an etching mask, and a desired metal interconnection is produced.
Referring to FIGS. 48 and 49, resist pattern 10d is removed and an interconnection constituting a part of a semiconductor device is formed.
According to the conventional method of forming patterns, two reticles, the first reticle 19 where the contact hole pattern is formed and the second reticle 21 where interconnection patterns 3b and 3e are formed are used.
A manufacturing error generated during fabrication of reticles influences the conventional method. In other words, when patterns are drawn in a retide by electron beam, positional accuracy of the patterns on the reticle is deteriorated by the influence of accuracy of the stage of an EB lithography system, a positional accuracy of scanning beam, the adhesion state of deposited matter in the column in the system, lithography of blanks (glass substrate) of the reticle.
When the conventional method is applied to a device having a capacity on the level with 256M DRAM, it is confirmed that an overlay error due to a manufacturing error among reticles is about 10-20 nm.
Next, a problem is described that arises when an overlay error is generated in the photolithography.
Reforming to FIG. 50, the portion represented by the reference character X.sub.1 corresponds to a region that should be opened. The portion represented by the reference character X.sub.2 corresponds to a location occupied by an opening when the overlay error is generated. A shift between X.sub.1 and X.sub.2 corresponds to the portion represented by the reference character Y.sub.1. As shown in FIG. 50, if patterning of an interconnection is executed with the overlay error generated, an interconnection having a pattern-shift Y.sub.2 as shown in FIG. 51 is consequently produced.
Although shift Y.sub.2 is generated in the lateral direction in FIGS. 50 and 51 as one example, various forms of shifts could be generated such as a shift in the direction of depth relative to the plane of the figure, for example. If such a form of shift is generated, the interconnection pattern will not be appropriately matched with a pattern of a higher layer, causing shortcircuit of the interconnections.
In order to reduce such a shift in overlay to achieve a higher overlay accuracy, a manufacturing error of reticles should be decreased. In addition, a method of generating patterns that restricts an influence due to the manufacturing error of reticles in generation of a resist pattern is necessary.